The present invention relates to a driver controller for controlling multiple data drivers in a display panel, such as a PDP (plasma display panel) or an LCD (liquid crystal display).
In recent years, as the use of display panels, such as PDPs and LCDs, has become widespread, the screen size and the definition thereof have been increasing at a rapid pace. These display panels have hundreds to thousands of signal lines in the horizontal and vertical directions and realize panel display by driving these signal lines by associated multiple data drivers and a scanning driver.
Typically, a plurality of data drivers are cascade-connected to form data driver modules and the driving thereof is controlled by a corresponding driver controller. The cascade connection reduces the number of signals driven in parallel, but in a high-definition display panel, the driver controller needs to drive signals which range from several dozens to more than one hundred. In addition, as the display panel screen size has been increased, the load capacitances between the driver controller and the data driver modules have been increased, which requires the driver controller to have high output drive capability.
However, at the time when the driver controller drives more than one hundred signals by using its high output drive capability, if these signal lines change concurrently in the same direction depending upon display data, large amounts of transient current flow in output buffers in the driver controller. This causes power supply voltage and ground voltage supplied to the driver controller to vary greatly, which results in noise adversely affecting the driver controller itself and the peripheral devices thereof.
Therefore, according to a conventional technique, a delay circuit is inserted for each output bit so as to delay the points in time when respective output data change, so that the transient currents instantaneously passing through the output buffers reach their peaks at different points in time. This reduces noise occurring due to variation in power supply voltage and ground voltage in the driver controller (see Japanese Laid-Open Publication No. 2003-8424).
With the increase in the display panel screen size, signal line skews, resulting from the increased load capacitances between the driver controller and the data driver modules, have been increasing, while the operating frequency has been raised as performance has been enhanced. It has thus become difficult to satisfy AC timing of the data driver modules.
However, for the above-described conventional technique, which uses the delay circuits to delay the points in time when the respective data change, it is difficult to achieve highly-precise phase control, because of ambient temperature, voltage variation, and other conditions. In addition, the conventional technique has the drawback of lacking a mechanism for adjusting AC timing.